Embodiments presented herein generally relate to issuing instructions in a processor, and more specifically, to interleaving instruction tags in the processor.
A conventional superscalar processor may issue instructions out-of-order with respect to a predefined program order. Because subsequent instructions are often dependent upon results of previous instructions, an issue queue in the processor may use a dependency tracking scheme to ensure that all data dependencies are followed. For instance, in one approach, the processor manages dependencies using instruction tags. At issue of an instruction in a given clock cycle to a given execution unit, the processor associates the instruction with an instruction tag that uniquely identifies the instruction within the processor. Further, during the same cycle, an execution unit may broadcast the instruction tag to the issue queue. Doing so wakes up instructions that are dependent on the associated instruction (i.e., indicates that source operands for the dependent instructions are ready) and prepares the instructions for subsequent issue.
However, instructions stored in the issue queue can have different latencies. That is, a given instruction may take a certain number of cycles to produce resulting data depending on an underlying operation of the instruction (e.g., whether the instruction corresponds to an add operation, subtract operation, divide operation, etc.). Another instruction may take relatively greater or fewer cycles to complete. Further, the processor may include multiple execution units. As a result, the number of instruction tags broadcast to the issue queue can be quite large. Consequently, performance of the processor may be affected due to an increase in silicon usage and power consumption.